The invention relates to a method for producing a vertical trench transistor, and to a vertical trench transistor.
Trench transistors are sufficiently known. These are MOS transistors in which a gate electrode is arranged in a trench extending into a semiconductor body. In this case, the gate electrode is insulated from the semiconductor body by a gate dielectric layer and serves for controlling a conducting channel in a body zone arranged between a source zone and a drift zone/drain zone of the transistor.
The switch behavior of a MOS transistor is crucially influenced by the gate-drain capacitance, which is also referred to as Miller capacitance. The gate-drain capacitance is formed by sections of the gate electrode and of the drift zone/drain zone which mutually overlap, and a section of the gate dielectric which lies between the sections. In this case, a switching delay of the transistor upon a transition from a conducting to a blocking state, and vice versa, is shorter, the smaller the capacitance. Since the switching losses of a transistor increase as the switching delay increases, a rapidly switching transistor, that is to say a transistor having a smallest possible gate-drain capacitance, is desirable with regard to reducing the switching losses.